1. Field of the Invention
The present invention relates to a tri-state delay-typed phase lock loop, more particularly, to the phase lock loop which automatically judges the phase and frequency of an input reference signal so as to synchronously generate an output synchronous signal, whereas the frequency and the phase of the output synchronous signal are identical to those of the input reference signal.
2. Description of the Prior Arts
The presently known digital phase lock loops are mostly serving the application for the communication signal processing, which is emphasized as a small signal usage, and vulnerable for its noisy inputs.
When a conventional digital phase lock loop is employed, the control method thereof is to use phase frequency detector to detect if the reference signal is set to be positive edge triggering or negative edge triggering so as to carry out the state change. Therefore, when said phase lock loop enters a steady state, if the reference signal is affected by exterior influences so as to cause the phase detector malfunction, correspondingly, the output synchronous signal generated by the phase lock loop will, in accordance with the malfunction, change its present state. The inevitable issue for avoiding the influence can be addressed by skilled person as the conventional digital phase lock loop locks its loop by using shift registers and counters for counting and generating a control signal, and the direction for counting and shifting follows the positive edge triggering and negative edge triggering after comparison with reference signal and synchronous signal to change the shifting direction or up-and-down signal, and there lacks a judge mechanism to suppress the malfunction due to the reference signal affected by exterior influence.
The conventional delay-typed phase lock loop, as long as its control delay unit is concerned, can be categorized as digital-typed, analog-typed, and digital-and-analog mixed-signal typed. For the digital-typed PLL, the control signal is stored in the registers, hence, when the circuit enters a sleep mode or is devoid of input signal, the signals recorded by said PLL will not disappear, alternatively, when the circuit restarts, said digital-typed PLL can achieve a locking state quickly. Various digital-typed PLLs are advantageous at fast locking, high process/supplying voltage tolerance, and more obvious while the process advances. However, since its delay is digitally controlled, the phase skew and jitter at locking state are getting worse while being compared with the conventional analog-typed PLL. In a digital-typed PLL a fixed byte of registers are applied, and its phase error is equivalent to a delay time that a delay unit can provide. If the phase skew and jitter are to be reduced, then the delay time that a delay unit can provide should be reduced, correspondingly, an operable frequency range, which a PLL can operate, is reduced. An ideal digital-typed PLL not only to be provided with a minimum phase skew and jitter, but also a maximum operable frequency range, however, it cannot be achieved within a limited die size, since the locking time is proportional to the counting of delay units and the wider the operating frequency range is, the longer its locking duration is needed.
Accordingly, in view of the above drawbacks, it is an imperative that a tri-state delay-typed PLL, which automatically adjusts the phase and frequency of the input reference signal and simultaneously generates an output synchronous signal identical to the input reference signal in their frequencies and phases, is designed so as to solve the drawbacks as the foregoing.